fence

Operands

imm, imm

Ensure that IO and memory accesses before the fence happen before the following IO and memory accesses as viewed by a different thread

Variants

Ensure that IO and memory accesses before the fence happen before the following IO and memory accesses as viewed by a different thread fence 1, 1

# Store 42, order reads and writes before reads and writes, then load 42 back. This single-threaded emulator cannot show ordering between harts.
.data
value: .word 0
.text
la t0, value
li t1, 42
sw t1, 0(t0)
fence 3, 3
lw t2, 0(t0)
1
2
3
4
5
6
7
8
9