SUBW: RISC-V instruction reference

subwSubtract word (32-bit) RV64 only
Subtracts the third register from the low 32 bits of the second and sign-extends the 32-bit difference into the first.
RISC-V manual: subw 
Forms  subw , ,   
Operands t1 Any integer register, x0 to x31, or its named alias, such as zero, t0 or t6. 
t2 An integer register. It may be the same register as t1. 
t3 An integer register. It may be the same register as t1. 
This example runs on RV64.
 .text
li t0, 13
li t1, 5
# t0=13, t1=5; subw writes 8 to t2.
subw t2, t0, t1